Shift Register

Basic functionality of shift register is to provide delay chain to data bit. This delay is in terms of number of clocks. D flip-flops are used to introduce this delay, N D-flip-flops will introduce N clocks delay.

There are many application of shift-register! For example, to convert bits to byte, a 8-bit shift register can be used, where output data will be sampled after every 8 clocks.

Figure below shows how D-flip-flops are used to construct a 4-bit shift register.


From the above figure it is very clear that each D-flip-flop shall introduce 1 clock delay. One can see that, after first clock, input bit "bit_in" will move to "O1". On second clock edge, output at "O1" will move to "02" and a new bit from "bit_in" will move to "O1". Similarly, On third clock edge, output at "02" will move to "O3", "O1" will move to "O2" and "bit_in" will move to "O1".

Also note that input "bit_in" will be available at "O4" only after 4 clocks, hence a delay of 4 clocks has been introduced.