This is not simply a tutorial on VHDL, but it is a practical tutorial on VHDL. Here I won't cover each and every topic of the VHDL as a language; but one thing I will try to make sure that the topics explained here are enough for any one to have full feel of VHDL as a language and as a philosophy. Here we are not much bothered about the cute syntax, and different number of ways a statement can be coded stuff. But we are more interested in converting a problem (digital solvable) to a design solution, and its VHDL code.
Facts about VHDL : VHDL is not a general language as C, C++ or JAVA, but a very specific language used to represent digital logic for digital systems. Hence, in this tutorial we will first learn how to represent various digital component such as flops, latches, adder subtracter, registers, clock etc in VHDL. After all any digital design is merely a placement of these component in such a way that they provide a solution.
How to run a VHDL design : Any vhdl design is either targeted for ASIC (Application specific integrated circuit) or FPGA (Field programmable gate arrays), but before one sends his design to ASIC foundry to get his design converted in to chip, or for FPGA solution, designer converts his design into bit file, program's FPGA and provides instant solution. The design should be syntactically and logical correct. To check your syntax and logical issues you need a software called VHDL Simulator. These simulator simulates your design as a real life digital design, and takes care of all concurrency. Since in any design, multiple components work parallely and it is simulator's job to model this concurrent behavior properly to create a real life situation. They also provide great debugging tools such as waveforms, breaks etc. There are many free to try simulator available by various vendors, since their commands are simulator specific, you may need to read there manual before you run your design.
Your are not done yet! : You thought a great design, wrote a good bug free code, and using simulator checked that logically every thing is correct as per your requirement. But this is not enough! To convert your design into actual hardware i.e For ASIC or FPGA. You need to break your design one more level down, and replace the whole design with only NOR gates and flip-flops. It is very important that functionally both the design should be same (originally coded and broken-down). This process of breaking your design is called synthesis. Synthesis also takes care of your design timings and some of the backend issues(which we will discuss later). Synthesis is not a manual task, but requires another special software generally referred as "synthesis tool". Synthesis tool reads your vhdl code and generates another broken-down design (in separate file). Its job of synthesis tool that there should not be any functional difference between both the designs. These synthesis tools are vendor and solution specific i.e ASIC or FPGA solutions. Some vendor provides synthesis tools along with their FPGA, but again the commands shall be tool specific.
Now you are familiar with the flow and we will look into another important topic of DESIGN Next