In digital electronics Clock and Resets are very-very important topics, and enough care should be taken from very initial phase of design itself.
For example, if the clock frequency is not taken care and after designing, coding, implementation, verification and synthesis you find that your design is unable to run at required frequency, then you are in real trouble. Are Your all efforts gone waste? May be! depending on the complexity of the design and severity of problem this may cost you a lot. Even you man need to change the architecture of some modules. Don't get afraid, we will discuss these issues later, so that you will face minimum problem.
First, lets see how to code clock and reset in vhdl..
Coding clock in VHDL is really a cakewalk, we need to write only two line of code.
First declare a signal clock with initial value to '0'
SIGNAL clock : STD_LOGIC := '0';
Now since we want to generate a clock of 10us time period, we will toggle clock every 5us as shown in the code below.
clock <= NOT clock AFTER 5us;
Coding RESET is also similar and straight forward...
Since, we want that initially our design should be under reset, we will declare signal a reset keeping its initial value to '0'
SIGNAL reset : STD_LOGIC := '0';
Now we want reset to remove after 100 us ..
reset <= '1' AFTER 100us;
Thats all about coding. But there are some tips about clock and reset which one should keep in mind while designing..
Remember that clock and reset cannot be synthesized. Any VHDL statement that uses after construct cannot be synthesized. Clock and reset should always come as inputs to your design, never attempt to generate them within your design! It not practical. Clock and reset generation discussed above can only be used for simulation purpose. Where you can instantiate a clock_generator module with your top design entity, and this clock generator will feed clock and reset to your design. We generally put clock generator module in the TEST_BENCH. The TEST_BENCH generates test vectors, clock and reset for the design for verification. Note that the TEST_BENCH should be excluded from synthesis.
NOTE: Here design is referred as code which will go into hardware (FPGA or ASIC)
- Always take clock frequency into account while designing, putting too much combinatorial logic may violate sample and hold timing and won't fit into clock's time period.
- Neglecting reset, or coding without reset is very bad idea. Always take reset into your design. Not considering rest may run that on the simulator, but may not run on the actual hardware.
- Never play around clock and reset. I mean, never put logic using clock or reset to meet the specification. Stuff like ANDing clock and data, or ANDing reset and data etc... Keep clock and reset clean.
- Make sure that the delay path of clock and reset should be same to all the blocks, otherwise you may face delta delay issues..
- Design whole project with either +ve or -ve edge clock, but stick to one.
- Same with the Reset, stick to one active value either '0' or '1' throughout the design.